CPU Core Design Verification Test Generator Lead (RISC-V)

Location: Hybrid, based in Austin, Texas, or Santa Clara, California, United States

Company

Tenstorrent develops high-performance AI computing platforms, including open RISC-V CPUs and related software, compiler, networking, and semiconductor technologies.

What you will do

• Lead development of core-level test generators for high-performance out-of-order RISC-V CPUs.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification across pre-silicon and post-silicon environments.
• Develop directed and randomized stimulus targeting architectural corner cases, instruction interactions, and complex CPU behavior.
• Support RISC-V certification through test content, compliance flows, debugging, and closure.
• Guide a team of 4–5 engineers while contributing hands-on to implementation, debugging, and verification execution.

Requirements

• 8+ years of experience in CPU design verification, test generation, or closely related CPU validation.
• Experience leading test generator development for x86, ARM, or RISC-V ISA environments.
• Strong understanding of CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture.
• Experience building tools, stimulus, and automation that scale verification across large CPU programs.
• Clear communication across design verification, design, architecture, emulation, and post-silicon teams.
• Eligibility to access U.S. export-controlled technology is required; employment may depend on citizenship, permanent residency, or prior license approval under U.S. export laws.

Culture & Benefits

• Collaborative environment focused on curiosity and solving technically difficult problems.
• Opportunity to work on open, state-of-the-art compute for real workloads and developers.
• Exposure to CPU core and cluster design, validation, certification, and broader AI compute programs.
• Employment offer and level are aligned with the candidate's assessed experience during the interview process.