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15 часов назад

Front End CAD Principal Engineer (Semiconductor)

150 680 - 225 700$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Front End CAD Principal Engineer (Semiconductor): Developing next-generation automated design flows and add-on tools for semiconductor solutions with an accent on modular CAD infrastructure and design methodology. Focus on optimizing RTL linting, equivalence checking, and driving architectural alignment across multiple business units.

Location: Santa Clara, CA; Irvine, CA; Austin, TX; San Diego, CA; Westborough, MA. Must be eligible to access export-controlled information as defined under U.S. law.

Salary: $150,680 - $225,700 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Develop and maintain leading-edge CAD flows to address the needs of various Business Units.
  • Deploy and support highly modular and automated CAD flows.
  • Collaborate with infrastructure and flow teams to ensure optimal integration within the overall CAD platform.
  • Create innovative solutions to solve increasing design challenges.
  • Lead stakeholder alignment across multiple BUs regarding key CAD architectural decisions.

Requirements

  • Bachelor's degree in CS, Electrical Engineering, or related field with 10-15 years experience (or Master's/PhD with 5-10 years).
  • Strong scripting skills in Tcl and Python for flow development.
  • Proficiency in Verilog and System Verilog Design and Verification.
  • Experience with RTL linting tools and clock domain crossing (CDC).
  • Experience with git revision control.
  • Must be eligible to access export-controlled information (EAR) as defined under U.S. law.

Nice to have

  • Knowledge of Equivalence Checking (LEC or Formality).
  • Experience with UPF definition and multiple power domains implementation.
  • Knowledge of RTL qualification, integration, and release processes.
  • Ability to write, validate, and debug timing constraints (SDC).
  • Knowledge of Synthesis tools and downstream integration with P&R tools.
  • Experience implementing Functional ECOs.

Culture & Benefits

  • Comprehensive financial well-being programs and an employee stock purchase plan with a 2-year look back.
  • Family support programs to help balance work and home life.
  • Robust mental and physical health resources.
  • Recognition and service awards for professional milestones.

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