RTL Design Sign Off Lead

TL;DR

RTL Design Sign Off Lead (VLSI): Defining and enforcing synchronization strategies for high-speed complex IPs in advanced process nodes with an accent on synthesis constraints, full-chip CDC/RDC methodology, and zero-defect silicon sign-off. Focus on reviewing testability, DFT design, clocking and reset architectures, identifying metastability issues, and driving automated flows for multi-site teams.

Location: USA-Colorado-Fort Collins (4380 Ziegler Road) or USA-CA San Jose (Innovation Drive)

Salary: $108,000 - $172,800 annual base

Company

Global technology leader designing, developing and supplying semiconductor and infrastructure software solutions.

What you will do

• Define and enforce synchronization strategies across multi-clock domains in advanced nodes.
• Own constraint creation for synthesis, CDC/RDC methodology, and waivers for zero-defect silicon.
• Collaborate with Architecture and Chip Lead teams to review DFT, clocking, and reset architectures early.
• Perform structural and functional verification of crossings using SpyGlass CDC/RDC, Spyglass Lint, JasperGold, Meridian.
• Mentor design team on Synthesis, DFT, CDC/RDC best practices and automate sign-off flows.

Requirements

• BSEE required, MSEE/PhD preferred
• 8+ years of related experience
• Deep expertise in Synthesis, DFT, CDC, RDC sign-off for high-speed IPs.
• Experience with SerDes, LPDDR5/6, DDR4/5, HBM interfaces.

Culture & Benefits

• Competitive base salary, discretionary annual bonus, new hire and annual equity awards.
• Medical, dental, vision plans, 401(K) with company matching, ESPP, EAP.
• Company paid holidays, paid sick leave, vacation time, Paid Family Leave.