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2 дня назад

Advanced Package Technology Distinguished Engineer (AI)

222 800 - 329 670$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Advanced Package Technology Distinguished Engineer (AI): Develop packaging technology roadmap for AI XPU, XPU-attach and Switch with an accent on signal integrity, power integrity, thermal integrity, and mechanical reliability. Focus on defining package architecture including chiplet topology, leading co-design efforts with silicon teams, and partnering with OSATs for process capability and volume readiness.

Location: Chandler, AZ; Austin, TX; Santa Clara, CA (onsite). US export control eligibility required (US citizens, permanent residents, or protected individuals).

Salary: $222,800 - $329,670 per annum (USD)

Company

hirify.global’s semiconductor solutions are essential building blocks for data infrastructure in enterprise, cloud, AI, and carrier architectures.

What you will do

  • Develop packaging technology roadmap for AI XPU, XPU-attach, and Switch, exploring beyond-current technologies and creating IP.
  • Define package architecture including chiplet topology, interposer scaling, PDN strategy, and thermal design; lead co-design across silicon, floorplanning, and reliability.
  • Perform signal/power integrity studies, routing feasibility, and optimization for 2.5D/3D packages.
  • Partner with OSATs, foundries, and vendors to evaluate manufacturability, yield, cost, and drive qualification to volume production.
  • Lead material selection, substrate stack-up, mechanical modeling, and reliability analysis.

Requirements

  • Bachelor’s in mechanical engineering, material science or related + 20+ years experience; or Master’s + 15+ years; or PhD/post-doc + 12+ years.
  • Deep experience in advanced package/substrate technologies, process/materials, reliability, warpage, thermal management.
  • Expertise in signal/power integrity simulations for 2.5D/3D packages (Cadence Sigrity PowerSI, Ansys SIwave/HFSS/Clarity).
  • Knowledge of interposer/substrate/PCB design rules, routing feasibility (Cadence APD/PCB editor), chip-package interactions.
  • Experience managing cross-functional programs, vendors, OSATs; strong communication for global stakeholders.
  • US work authorization for export-controlled technology.

Nice to have

  • Prior experience in data center AI accelerators, networking/HPC silicon, silicon disaggregation/memory integration.
  • Board/system/rack level integration, thermal/mechanical/signal/power analysis.
  • Experience setting roadmaps, influencing senior stakeholders/suppliers, VNA/TDR measurements.

Culture & Benefits

  • Comprehensive benefits: financial well-being (employee stock purchase plan), family support, mental/physical health resources, recognition awards.
  • Opportunity to impact innovation in AI, cloud, networking; work with global teams across time zones.
  • Collaborative environment focused on purposeful technology development.

Hiring process

  • Interviews evaluate experience, thought process, communication; no AI tools allowed (disqualification if used).
  • Contact HR for accommodations; export license review may apply.

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