SoC Logic Design Engineer (SystemVerilog)

TL;DR

SoC Logic Design Engineer (SystemVerilog): Developing RTL coding and simulation for SoC designs with an accent on integrating IP blocks and subsystems into full chip components. Focus on optimizing logic for power, performance, area, and timing goals while ensuring physical implementation integrity.

Location: Hybrid (US: Santa Clara, CA; Fort Collins, CO; Hillsboro, OR)

Salary: $141,910.00 - $269,100.00

Company

hirify.global's Data Center Group develops Xeon-based and custom x86 products for general-purpose compute, HPC, and AI-accelerated systems.

What you will do

• Perform RTL coding to meet functional, area, power, and timing goals.
• Execute quality checks including Lint, CDC, and Low Power checks.
• Collaborate with architects to define design requirements and write detailed micro-architectural specifications.
• Debug designs in simulation in close coordination with the verification team.
• Partner with the physical design team to ensure the design is physically implementable.
• Work with IP providers to integrate and validate IPs at the SoC level.

Requirements

• Bachelor's degree in Electrical/Computer Engineering or related STEM field with 6+ years of experience, or a Master's degree with 5+ years.
• Proven experience in SoC or Subsystem RTL design and integration using Verilog/SystemVerilog.
• Location: Must be based in the US (Santa Clara, Fort Collins, or Hillsboro) for a hybrid work model.

Nice to have

• Experience with SoC flows for Reset, Power Management, Interrupts, and Error Handling.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive benefit programs covering health, retirement, and vacation.
• Hybrid work model allowing a split between on-site and off-site work.
• Opportunity to work on next-generation hirify.global SOCs within the Data Center Group.