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1 день назад

Senior Staff SoC Design Engineer (AI)

134 390 - 201 300$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff SoC Design Engineer (SystemVerilog/RTL): Designing and integrating high-performance SoC microarchitecture for next-generation AI interconnects with an accent on PPA targets, memory interfaces, and full-chip integration. Focus on implementing complex IP, optimizing data flow for AI accelerators, and ensuring design sign-off for tape-out.

Location: Santa Clara, CA (Onsite)

Salary: $134,390 - $201,300 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Define microarchitecture and develop SystemVerilog RTL for SoC components, including interconnects, memory interfaces, and global logic.
  • Integrate processor clusters, HBM/DDR memory controllers, and high-speed interfaces, focusing on data flow and system-level behavior.
  • Collaborate with verification teams to review test plans, support functional debug, and close coverage gaps.
  • Perform design checks (lint, CDC/RDC), define timing constraints, and work with physical design teams to meet implementation requirements.
  • Coordinate with IP, SerDes, and analog teams to integrate complex interfaces and resolve subsystem issues.
  • Contribute to design methodology and provide technical guidance to other engineers.

Requirements

  • Bachelor’s degree in CS or EE with 5-10 years of experience, or Master’s/PhD with 3-5 years of experience.
  • Proven experience delivering complex SoCs to tape-out and working across subsystem boundaries.
  • Strong RTL design skills in SystemVerilog and hands-on experience with SoC integration and debug.
  • Familiarity with AMBA protocols (AXI), SoC interconnect architectures, clock/reset design, and CDC.
  • Understanding of how RTL decisions impact physical implementation.
  • Experience with Python or Tcl scripting for automation.

Nice to have

  • Exposure to emerging interconnect standards such as UCIe and UALink.

Culture & Benefits

  • Financial well-being programs, including an employee stock purchase plan with a 2-year look back.
  • Comprehensive family support programs to help balance work and home life.
  • Robust mental and physical health resources.
  • Recognition and service awards to celebrate contributions and milestones.

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