IC Design Engineer (DFT)

TL;DR

IC Design Engineer (DFT) (ASIC): Developing state-of-the-art IC solutions utilizing CMOS cell-based ASIC technologies with an accent on DFT architecture, synthesis, and timing verification. Focus on implementing scan, MBIST, and Logic BIST for 5nm/3nm designs and debugging DFT patterns on ATE.

Location: Shanghai, China (Onsite)

Company

hirify.global is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Participate in chip-level DFT architecture definition.
• Implement basic DFT schemes, including scan, boundary scan, MBIST, Logic BIST, and SSN.
• Verify all DFT logics and test patterns through simulation.
• Perform static timing analysis (STA) for test modes.
• Participate in ATE bring-up and debug DFT patterns on ATE.
• Work on advanced 5nm/3nm designs.

Requirements

• Bachelor or Master degree in Microelectronics or a related discipline.
• 5+ years of related experience required.
• Strong understanding of General DFT methodology (BIST, SCAN, JTAG, and ATPG).
• Familiarity with Mentor and Synopsys DFT flow and tools.
• Experience in developing constraints for synthesis and STA.
• Expertise in multi-mode, multi-corner STA and understanding of Sign-Off Checks.

Culture & Benefits

• Opportunity to work with leading-edge 5nm/3nm CMOS cell-based ASIC technologies.
• Career growth within a global technology leader.
• Collaborative environment working with both internal and external customers.
• Committed equal opportunity employer.