Principal Microarchitect (AI)

TL;DR

Principal Microarchitect (AI/Silicon): Designing data movement pipelines and SoC architecture components for next-generation AI infrastructure with an accent on performance-per-watt optimization for inference. Focus on defining datapaths, optimizing power and area, and debugging real silicon issues to enable large-scale model efficiency.

Location: Santa Clara, CA; New York City, NY; San Francisco, CA

Salary: $250,000–$325,000

Company

An early-stage startup backed by a Tier-1 VC that is rethinking AI infrastructure from first principles to deliver superior performance-per-watt for inference.

What you will do

• Design data movement pipelines, scheduling algorithms, and control logic to integrate SoC architecture components.
• Define datapaths including scratchpads memories, buffers, NoCs, and crossbars.
• Use performance modeling and profiling to guide architecture decisions and optimize for power and area.
• Collaborate closely with compiler, kernel, and performance teams to evaluate ISA and programming model trade-offs.
• Support RTL implementation, verification, timing closure, and post-silicon performance tuning.
• Debug real silicon issues to close performance gaps.

Requirements

• Expert understanding of NoCs, buffering, switches, memories, crossbars, and scheduling.
• Direct experience in AI compute or accelerator design.
• Proven track record of delivering real silicon across multiple generations of process technology.
• Strong experience in performance-per-watt optimization.
• MS or PhD with 5-10 years of experience, or equivalent.

Nice to have

• Experience working within startup or early-stage silicon programs.

Culture & Benefits

• Opportunity for massive ownership and significant impact.
• Ability to build high-performance AI infrastructure from the ground up.
• Working with a team of industry veterans with a track record of shipping successful products.