Senior FPGA Design Engineer (FPGA)

TL;DR

Senior FPGA Design Engineer (FPGA/Verilog): Design and implement RTL logic for complex high-speed designs with an accent on timing closure, synthesis, and backend development. Focus on translating high-level requirements into detailed specifications and performing system-level lab bring-up.

Salary: $120,000 – $170,000

Company

hirify.global specializes in ASIC and FPGA design, verification, and embedded software development services, augmenting client teams to accelerate complete designs.

What you will do

• Translate high-level requirements into detailed technical specifications.
• Design and implement RTL logic using Verilog or SystemVerilog.
• Execute block-level simulation, FPGA synthesis, backend processes, and timing closure.
• Collaborate with verification, design, hardware, and support teams.
• Conduct lab bring-up and product integration.
• Provide technical support to customers for complex technical issues.

Requirements

• Minimum 8 years of relevant experience in the FPGA design field.
• Proficiency in high-speed FPGA Design Flow using Verilog and SystemVerilog.
• Experience with Xilinx Vivado/FPGA families or Intel Quartus/Agilex.
• Expertise in complex asynchronous clock boundaries and high-speed serial interfaces.
• Experience troubleshooting issues in a lab environment up to the system level.
• Knowledge of industry interfaces such as Ethernet, PCIe, SPI, I2C, USB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, 4G, LTE, 5G, O-RAN, and 3GPP.

Nice to have

• Test verification and scripting experience.
• Software development background.

Culture & Benefits

• Competitive salary dependent on individual experience and capability.
• Company bonus plan.
• Comprehensive benefits plan.