Staff/Principal Analog/Mixed-Signal Design Engineer (SerDes)

TL;DR

Staff/Principal Analog/Mixed-Signal Design Engineer (SerDes): Own and implement analog/mixed-signal and full-custom building blocks for high-speed data interfaces with an accent on SerDes, PLLs, Rx/Tx analog frontends, and digital control loops. Focus on designing circuits including schematics, simulations, collaborating with architects, verification, and layout teams, and leading design reviews.

Location: Hybrid in Mannheim (Germany) or Villach (Austria), or remote from Greece, Italy, Austria, Germany. Open to other EU countries; relocation support available, including visa assistance for non-EU.

Company

Leader in high-speed SerDes IP and interconnect technologies for semiconductor chips, driving chiplet-era innovations.

What you will do

• Own analog/mixed-signal, digital, and full-custom building blocks and subsystems.
• Design and implement circuits including schematics, testbenches, and simulations.
• Derive block-level specifications with system architects.
• Create models for verification team and guide layout team on physical implementation.
• Lead smaller design sub-teams and organize design reviews.
• Collaborate cross-functionally for on-time product releases.

Requirements

• B.S./M.S. in Electrical Engineering, Physics, or related with hardware focus.
• Min. 10 years experience, including high-speed SerDes or related (PLLs, Rx/Tx frontends, full-custom logic).
• Experience in mixed-signal designs with digital control loops.
• Familiarity with Cadence flow (Virtuoso, ADE, Spectre).
• Good English communication skills.

Nice to have

• Advanced nodes (FDSOI, FinFET).
• Scripting in Python/TCL.

Culture & Benefits

• Flexible hours, above-average vacation, worktime account, hybrid/remote options.
• Competitive salary (14 payments/year in Austria per collective agreement).
• Job security, career growth, further training.
• Team events, great atmosphere, football table, free drinks.
• Workation up to 6 weeks/year abroad.