ASIC DFT Engineer

TL;DR

ASIC DFT Engineer: Leading DFT programs from chip-level specification through implementation, verification, and production release for hirify.global's SoC designs with an accent on scan compression, MBIST, ATPG patterns, and yield improvement. Focus on DFT architecture design, test vector generation and debug, post-silicon validation, and innovating solutions for 3nm+ nodes.

Location: USA - California - San Jose (1320 Ridder Park Drive)

Salary: $141,300 - $226,000 annual base

Company

Global technology leader designing, developing, and supplying semiconductor and infrastructure software solutions.

What you will do

• Define DFT specifications based on hirify.global and customer requirements, including DPPM goals.
• Implement DFT features like scan, MBIST, TAP, LBIST, IO, SerDes integration.
• Generate, verify, and debug test vectors at chip level and on ATE.
• Collaborate with STA, physical design, and IP DFT teams for timing closure and design integration.
• Support silicon bring-up, failure analysis, diagnostics, RMA, and yield improvements.
• Interface with global customers, test engineering, and manufacturing teams.

Requirements

• Bachelor's +12 years or Master's +10 years in related experience
• Strong DFT expertise in scan compression, ATPG, BIST (Logic/Memory), IO/Analog DFT.
• Experience with tools: DFT Compiler, TestKompress, TetraMax, Fastscan.
• Verilog coding, testbench development, simulation.
• Knowledge of IEEE1149.1/1149.6, IEEE1687/IJTAG, Test-STA constraints.
• Analog/digital circuit fundamentals, silicon processing, synthesis, reliability.
• Excellent debug, problem-solving, communication, and project management skills.

Nice to have

• ATE experience.
• SerDes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug.
• Tessent SSN experience.

Culture & Benefits

• Competitive base salary, discretionary annual bonus, new hire and annual equity awards.
• Comprehensive benefits: medical, dental, vision, 401(k) with matching, ESPP, EAP.
• Paid holidays, sick leave, vacation, family leave per applicable laws.