Superconducting Chip Design Internship H/F

TL;DR

Superconducting Chip Design Internship: Design and simulate testbeds for quantifying internal loss sources in superconducting qubits with an accent on FEM tools and material interface analysis. Focus on developing measurement methodologies, chip designs, and qubit optimization guidelines for maximum lifetimes.

Paris

Company

Developing the first universal, fault-tolerant quantum computer based on Schrödinger cat qubits.

What you will do

• Review methods for estimating energy participation ratios in superconducting circuits.
• Design and simulate testbed using FEM tools like Ansys HFSS to measure internal chip loss.
• Design superconducting chips to validate testbed and extract loss from material interfaces.
• Design chip-testbed interfaces, including dilution refrigerator wiring integration.
• Plan test chip integration into fabrication processes.
• Develop measurement and analysis methods to quantify interface loss contributions.
• Collaborate with circuit designers to provide qubit design guidelines from simulations.
• Document methods, scripts, results; present in meetings and design reviews.

Requirements

• Currently enrolled in Master's in Engineering or Physics.
• Available for 5-6 months internship, ideally from August 2026.
• Prior knowledge of electromagnetic field theory.
• Hands-on experience with electromagnetic solvers (e.g., Ansys).
• Experience with Python.
• Proficient English skills, written and spoken.
• Strong curiosity, openness to ideas, research skills.

Culture & Benefits

• 1 day off per month.
• Half transportation cost coverage (per French law).
• Meal vouchers with Swile, equipped kitchen.
• Passionate, friendly team in innovative French startup.
• Space to innovate, develop ideas, and grow.