Physical Design Engineer (AI)

TL;DR

Physical Design Engineer (AI/Silicon): Architecting and optimizing power intent and delivery networks for next-generation AI accelerators with an accent on multi-voltage SoC design and EMIR methodologies. Focus on developing automated UPF and power grid flows and ensuring robust silicon delivery on leading-edge FinFET nodes.

Location: Hybrid; must be based in Santa Clara, CA, Austin, TX, or Fort Collins, CO

Salary: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, revolutionizing performance expectations and cost efficiency through high-performance RISC-V CPUs.

What you will do

• Architect and optimize power intent and delivery networks that form the backbone of AI accelerators.
• Own the development and automation of UPF and power grid flows.
• Define and deploy EMIR methodologies to deliver robust, scalable power solutions.
• Collaborate with world-class EDA partners and silicon architects to influence tooling and methodologies.
• Manage the complete RTL-to-GDSII lifecycle for advanced chips.

Requirements

• 5+ years of hands-on experience in CAD, methodology, or physical design for multi-voltage and low-power SoCs.
• Mastery of UPF-based power intent, power grid architecture, and EMIR analysis using tools like RedHawk and Voltus.
• Advanced scripting abilities in Tcl, Python, and Perl for architecting automated flows.
• Proven impact delivering robust solutions on leading-edge FinFET nodes.
• Must be eligible to access U.S. export-controlled technology (contingent on citizenship, permanent residency, or license approval).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Opportunity to work on breakthrough AI/ML accelerators and silicon platforms.
• Collaborative environment focused on solving hard problems with a world-class team.
• Exposure to state-of-the-art techniques in power grid construction and EMIR sign-off.