Design Verification Engineer (Automotive Robotics)

TL;DR

Design Verification Engineer (SystemVerilog/UVM): Leading verification efforts for state-of-the-art digital designs with an accent on verification strategy and advanced test environments. Focus on defining comprehensive verification plans, mentoring engineers, and ensuring the functional quality of AI compute engines.

Location: Remote, based in Munich, Germany

Company

hirify.global is an AI technology company developing high-performance RISC-V CPUs and AI accelerators based on a chiplet architecture.

What you will do

• Define and execute comprehensive verification plans for complex digital blocks and systems.
• Drive verification methodologies and strategy across projects, setting standards and best practices.
• Build advanced test environments using SystemVerilog and UVM.
• Collaborate with architecture, design, and software teams to align specifications and debug issues.
• Guide and mentor junior engineers to foster a high-performing verification team.

Requirements

• 10+ years of industry experience in digital design verification with technical leadership record.
• Deep expertise in SystemVerilog, UVM, and familiarity with formal verification methods.
• Strong understanding of computer architecture, microarchitecture, and SoC integration.
• Hands-on experience with simulation environments such as Questa or VCS.
• Must be based in Munich, Germany.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).

Culture & Benefits

• Highly competitive compensation package.
• Innovation-first culture focused on solving hard problems in AI and high-performance compute.
• Collaborative environment working with top-tier hardware architects.
• Equal opportunity employer.