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3 дня назад

Principal Physical Design Engineer (ASIC)

173 800 - 257 190$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Principal Physical Design Engineer (ASIC): Driving RTL-to-GDSII implementation and methodology for next-generation high-performance processor chips with an accent on PPA optimization and signoff quality. Focus on solving complex congestion and timing challenges in leading-edge CMOS process technologies for server and networking applications.

Location: Westborough, MA. Applicants must be eligible to access export-controlled information as defined under U.S. law.

Salary: $173,800 - $257,190 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Lead RTL-to-GDSII implementation for complex blocks, encompassing synthesis, floorplanning, PnR, CTS, and timing closure.
  • Drive improvements in physical design methodologies and automation to enhance productivity and signoff quality.
  • Solve critical technical challenges regarding congestion, signal integrity, and design-rule issues.
  • Collaborate with RTL, STA, and verification teams to influence micro-architecture and design decisions.
  • Mentor junior engineers and establish best practices within the physical design organization.
  • Partner with EDA vendors to evaluate new features and drive tool enhancements.

Requirements

  • Bachelor's degree in EE/CS with 5-10 years of experience, or Master's/PhD with 3-5 years of experience.
  • Proven track record of driving physical design for large, high-performance chips and successful tape-outs.
  • Deep expertise in hierarchical physical design strategies and advanced-node implementation.
  • Strong understanding of the ASIC design flow and current foundry technologies.
  • Proficiency in automation scripting using Tcl, Python, or Perl.
  • Eligibility to access export-controlled information under U.S. export control laws (EAR).

Nice to have

  • Familiarity with AI/ML-driven optimization in physical design tools.
  • Experience with PrimeTime, Tempus, Voltus, Redhawk, Quantus, StarRC, or Calibre.

Culture & Benefits

  • Employee stock purchase plan with a 2-year look-back.
  • Comprehensive financial well-being and family support programs.
  • Robust mental and physical health resources.
  • Recognition and service awards for career milestones.
  • Supportive environment designed to balance work and home life.

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