Design Verification Engineer (Semiconductor)

TL;DR

Design Verification Engineer (SystemVerilog/UVM): Verifying complex, high-performance digital IP and SoC designs for next-generation semiconductor products with an accent on DDR protocols and UVM methodology. Focus on creating detailed test plans, executing verification at block and system levels, and ensuring high-quality coverage closure.

Location: Thessaloniki or Athens, Greece

Company

Global leader in consulting, technology services, and digital transformation.

What you will do

• Develop and maintain UVM-based verification environments for digital IP and subsystems.
• Create detailed test plans, testbench components, sequences, and functional coverage models.
• Execute verification at block, subsystem, and system levels and debug issues using waveform viewers.
• Verify and validate DDR memory controller or PHY interfaces, ensuring compliance with industry standards.
• Collaborate with architects and designers to review specifications and identify corner cases.
• Drive improvements in verification methodology, automation, and overall efficiency.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of hands-on experience in ASIC/FPGA design verification.
• Strong skills in SystemVerilog and UVM methodology.
• Proven experience with DDR protocol verification (DDR3, DDR4, LPDDR4/5, or DDR5).
• Proficiency with simulation and debugging tools such as VCS, Questa, or Incisive.

Culture & Benefits

• Opportunity to work within the specialized Products & Systems Engineering domain.
• Integration into a large-scale global team and professional environment.
• Supportive recruitment process with dedicated interview tips and guidance.