Design Verification Engineer (SystemVerilog/UVM)

Location: Ampelokipoi, Athens, or Thessaloniki/Steliou Kazantzidi, Greece

Company

hirify.global is hiring for semiconductor design verification work focused on digital IP and SoC products.

What you will do

• Develop and maintain UVM-based verification environments for digital IP and subsystems.
• Create test plans, testbench components, sequences, and functional coverage models.
• Execute verification at block, subsystem, and system levels, including regressions and coverage closure.
• Debug design and verification issues using waveform viewers and simulation tools.
• Review specifications with architects and designers to identify corner cases.
• Verify DDR memory controller and PHY interfaces for standards compliance while improving verification automation and methodology.

Requirements

• 5+ years of hands-on ASIC/FPGA design verification experience.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong SystemVerilog and UVM methodology skills.
• Solid understanding of digital design fundamentals and proven DDR protocol verification experience with DDR3, DDR4, LPDDR4/5, or DDR5.
• Proficiency with simulation, regression, and debugging tools such as VCS, Questa, or Incisive.
• Excellent problem-solving and communication skills.

Culture & Benefits

• Collaboration with architects, designers, and verification engineers.
• Work on high-performance digital IP and SoC designs for next-generation semiconductor products.
• Focus on stringent performance, reliability, and verification quality requirements.