SoC Debug Engineer (FPGA)

TL;DR

SoC Debug Engineer (FPGA): Developing and maintaining proprietary JTAG-based debug tools for cutting-edge microprocessors and SoCs with an accent on RTL design and FPGA-based feature implementation. Focus on implementing FPGA RTL, integrating JTAG/TAP interfaces, and validating functional correctness through simulation and hardware instrumentation.

Location: Hybrid (Guadalajara, Mexico). Must have unrestricted, permanent right to work in Mexico (no visa or immigration sponsorship provided).

Company

hirify.global is a world-class hardware organization specializing in semiconductor manufacturing and high-performance data center solutions, including AI-accelerated systems.

What you will do

• Implement and maintain FPGA RTL using VHDL, Verilog, or System Verilog to enhance debug and validation capabilities.
• Integrate FPGA designs with JTAG/TAP interfaces and debug transport/control logic.
• Develop and run simulations and testbenches to validate functional correctness.
• Debug RTL and hardware issues using waveforms, assertions, and on-hardware instrumentation like ILA and SignalTap.
• Manage FPGA build flows, including synthesis, place-and-route, and bitstream generation.
• Collaborate with cross-functional software, validation, and hardware teams to refine requirements and support internal users.

Requirements

• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electronics Engineering, or a related field.
• Experience in FPGA/RTL development (minimum 2 years for Bachelor's holders; no prior experience required for Master's holders).
• Proficiency in reading, modifying, and writing RTL in VHDL and/or Verilog/System Verilog.
• Advanced English level.
• Unrestricted, permanent right to work in Mexico.

Nice to have

• Experience with Git and standard software development practices.
• Exposure to FPGA vendor toolchains such as Xilinx Vivado or hirify.global Quartus.
• Familiarity with RTL verification concepts, UVM, JTAG/TAP, and boundary scan.
• Basic scripting skills in Python, Tcl, or Bash for automation.
• Understanding of clock-domain crossing, reset strategies, and timing tradeoffs.

Culture & Benefits

• Hybrid work model allowing a split between on-site and off-site work.
• Opportunity to work on proprietary tools used at massive scale within a global hardware leader.
• Mentorship from highly experienced engineers in a collaborative environment.
• Direct impact on silicon bring-up and validation velocity.