Design Verification Senior Staff Engineer (ASIC)

TL;DR

Design Verification Senior Staff Engineer (ASIC): Driving functional verification of complex networking blocks for next-generation network switches with an accent on UVM and SystemVerilog. Focus on developing advanced verification components, maintaining testbenches, and implementing coverage-driven verification.

Location: Petah-Tikva, Israel

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Drive functional verification of complex networking blocks using UVM/SystemVerilog.
• Develop and maintain advanced verification components and testbenches.
• Collaborate with cross-functional teams, including architecture, design, firmware, and post-silicon.
• Contribute to methodology and infrastructure improvements in a dynamic environment.

Requirements

• B.Sc. or M.Sc. in Electrical/Computer Engineering.
• 7+ years of hands-on experience in ASIC/RTL verification.
• Strong background in SystemVerilog and UVM methodology.
• Deep understanding of coverage-driven verification, object-oriented programming, and constrained random testing.
• Must be eligible to access export-controlled information as defined under U.S. export control laws (EAR).

Culture & Benefits

• Competitive compensation and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Access to tools and resources designed for professional growth and development.