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Senior Serdes System Design Engineer/Architect

108Β 000 - 192Β 000$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR

Senior Serdes System Design Engineer/Architect: Designing and implementing advanced signal processing algorithms for high-speed Serdes products with an accent on PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters. Focus on implementing algorithms in advanced silicon technology nodes and validating designs for high-volume production.

Location: USA-TX-Austin, USA-CA San Jose, USA-CA Irvine

Salary: $108,000 - $192,000

Company

hirify.global is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

  • Develop channel models and run simulations to help define Serdes architecture.
  • Define and document signal processing block requirements, architecture, and lab test plan.
  • Develop bit-exact MATLAB and C/C++ system models for simulation and verification.
  • Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs.
  • Work with the design team to perform vector matching verification with RTL simulations.
  • Lab testing and debug of Serdes.

Requirements

  • B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required.
  • Expert knowledge in Communication Theory and Digital Signal Processing algorithms.
  • Working knowledge of Analog circuit behavior and Transmission line theory and s-parameter.
  • Expert in MATLAB, C/C++ programming.
  • Good hands-on skills in the lab.

Nice to have

  • Experience in designing high-speed Clock and Data Recovery (CDR) PLLs.
  • Experience in equalization techniques for wireline communication applications such as read-channel.
  • RTL coding skills.
  • Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards.

Culture & Benefits

  • Eligible for a discretionary annual bonus and the opportunity to receive competitive new hire equity grant, and annual equity awards.
  • Comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
  • The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’