Senior Design Verification Engineer

TL;DR

Senior Design Verification Engineer: Owning end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff with an accent on testbench architecture, test plan and coverage closure. Focus on driving convergence of simulation and formal verification into unified bug hunting and coverage closure strategies, evaluating and adopting emerging methodologies including ML-driven verification flows.

Location: US, California, Santa Clara. This role will require an on-site presence.

Salary: $190,610.00-269,100.00

Company

hirify.global is a technology company that creates world‑changing technology that improves the life of every person on the planet.

What you will do

• Own verification planning and execution for key IP features across IP and subsystem integration points.
• Build scalable verification environments and targeted testplans with reusable testbenches, checkers, VIPs, and behavioral models.
• Collaborate closely with architecture, design, and software teams from specification through bringup.
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics.
• Lead IP delivery to multiple customers while ensuring technical excellence.
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows.

Requirements

• Bachelor's Degree in Electrical Engineering, Computer Science, or related field, with 9+ years of relevant experience OR Master's degree in Electrical Engineering, Computer Science, or related field, with 6+ years of relevant experience in design verification.
• Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models.
• Demonstrated experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security features.
• Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation.
• Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C++, Python, and build systems; comfort using AI-assisted development tools as part of everyday workflow.
• Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule.

Nice to have

• 12+ years of relevant experience in design verification.
• Hands-on experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining formal and simulation for unified bug closure.
• Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks.

Culture & Benefits

• Competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.