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1 дСнь назад

Ip Design Verification Engineer

122Β 440 - 172Β 860$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
hybrid
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
middle
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify RU Global, списка ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ с восточно-СвропСйскими корнями
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR

IP Design Verification Engineer: Validating IP or features at the IP level for leading client SOCs with an accent on creating plans and tests for validating portions of a complex microarchitecture. Focus on debugging failures to the root cause, developing debugging tools and software, and implementing validation plans to ensure a solid design.

Location: US, Oregon, Hillsboro. This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned hirify.global site and off-site.

Salary: $122,440.00-172,860.00

Company

hirify.global's Devices Development Group is responsible for creating leading Client SOCs.

What you will do

  • Validate an IP or feature at the IP level.
  • Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
  • Learn architecture and microarchitecture by debugging failures to the root cause.
  • Develop and utilize various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
  • Engage with IP providers and customers to define, develop, and deliver necessary infrastructure and address issues found during execution.
  • Develop tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible.

Requirements

  • Must have either a BS + 2 years' experience or MS + 1 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
  • Minimum 2 years experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
  • Minimum 2 years experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog and OVM/UVM.
  • Minimum 2 years experience with writing validation plans and software to implement those validation plans.
  • Minimum 2 years experience with an object oriented programming language.
  • Minimum 1 years experience with UNIX or Linux.

Nice to have

  • Minimum 1 years experience with computer architecture.
  • Minimum 2 years experience with validation or testing experience, especially in a silicon design team.

Culture & Benefits

  • Total compensation package that ranks among the best in the industry.
  • Competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’