Senior Analog Validation/Characterization Engineer

TL;DR

Senior Analog Validation/Characterization Engineer: Performing hands-on validation of high-speed transceiver silicon and developing behavioral models to speed up chip simulation with an accent on hardware validation and AMS modeling. Focus on automating lab measurements, debugging silicon issues, and correlating lab results with simulation data.

Location: San Jose (Holger Way)

Salary: $166,200 to $228,500 annually (base salary range specific to California)

Company

hirify.global N.V. enables a smarter, safer, and more sustainable world through innovation.

What you will do

• Create and maintain behavioral models (SystemVerilog/RNM, Verilog-A) for mixed-signal blocks.
• Perform bench-top characterization of high-speed transceivers (10G+).
• Develop and optimize Python scripts to automate lab measurements and generate validation reports.
• Run mixed-signal co-simulations to verify connectivity and basic functionality of analog-digital interfaces.
• Collaborate with Design and Verification teams to debug silicon issues.

Requirements

• BSEE or MSEE with 3+ years of experience in IC modeling, design, or validation.
• Experience with Cadence Virtuoso, Spectre, or similar mixed-signal simulation environments.
• Proficiency in SystemVerilog (Real Number Modeling preferred) or Verilog-A.
• Hands-on experience with high-speed lab equipment for signal integrity and performance testing.
• Strong Python skills for automation.

Nice to have

• Familiarity with high-speed serial standards (e.g., SerDes, Ethernet, or PCIe).
• Experience working within a structured Product Development Process (PDP) in a large-scale semiconductor environment.
• Understanding of basic signal integrity concepts (jitter, eye diagrams, insertion loss).

Culture & Benefits

• Company benefits include health, dental, and vision insurance.
• 401(k) and paid leave.
• Career development opportunities.
• Commitment to sustainability and an inclusive work environment.

Hiring process

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