Dft Design Engineer

TL;DR

Dft Design Engineer (SoC/ASIC): Designing and implementing Design for Test (DFT) solutions for complex SoCs and ASICs with an accent on DFT insertion flows and memory build-in self-test (MBIST). Focus on Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals and debug failures.

Location: Must be US citizen. Onsite in Austin.

Company

hirify.global hires and develops leaders and innovators who want to make an impact on the world of technology.

What you will do

• Implement DFT insertion flows.
• Perform scan chain insertion using synthesis or other software tools.
• Work with compression scan insertion, LBIST and other scan technologies.
• Implement memory build-in self-test (MBIST).
• Perform Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals.
• Debug and analyze failures to improve fault coverage.

Requirements

• Must be US citizen
• 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT).
• Intimate knowledge of DFT insertion flows.
• Experience in compression scan insertion, LBIST and other scan technologies.
• Intimate knowledge of memory build-in self-test (MBIST).
• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals.

Nice to have

• Knowledge of timing analysis and equivalency checks would be added bonus
• Prior experience with hirify.global tools and flows is highly desirable

Culture & Benefits

• Work in collaborative team environment.
• Work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers.
• Self-driven and committed individual who can work in a fast-paced project environment.