Cpu Core Timing And Automation Engineer

TL;DR

CPU Core Timing and Automation Engineer: Performs timing analysis and optimization at chip/block level for SoCs with an accent on timing model generation and constraint management. Focus on driving timing closure across physical design stages, innovating with AI-based tools, and ensuring high-quality timing models.

Location: Hybrid work model, must be located in Folsom, California, USA

Salary: $105,650.00-200,340.00 USD

Company

hirify.global is a data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement, Custom ASIC, and Foundry Enablement.

What you will do

• Perform timing analysis and timing optimization for SoCs at chip/block level.
• Conduct timing rollups and design for functionality.
• Develop methodologies to ensure high-quality timing models.
• Collaborate with architecture, clocking design, and logic design teams.
• Build and maintain automation environments for timing model generation.
• Support backend platforms to resolve timing violations.

Requirements

• Bachelor’s Degree in Electronics, Electrical, Computer Engineering or a related field.
• 1+ years of experience in scripting and software development (TCL, Python, AI-based coding tools).
• At least a year of experience in backend design: synthesis, place and route (P and R).
• At least a year of experience with optimization flows of STA tools.

Nice to have

• 2+ years of experience in x86 CPU architecture.
• Experience with TCL/Perl/Python programming.

Culture & Benefits

• Competitive pay, stock bonuses, and benefit programs including health, retirement, and vacation.
• Eligible for a hybrid work model splitting time between on-site and off-site work.