Senior Principal DFT Design Engineer (DFT)

TL;DR

Senior Principal DFT Design Engineer (DFT): Designing and optimizing Design for Test (DFT) solutions for SoC/ASIC digital designs with an accent on scan chain insertion, compression scan technologies, memory built-in self-test (MBIST), and automatic test pattern generation (ATPG). Focus on achieving design test coverage goals, debugging failures, and verifying ATPG testbenches.

Location: Onsite in Austin, US. US citizenship required.

Company

hirify.global hires and develops leaders and innovators who want to make an impact on the world of technology.

What you will do

• Design and implement Design for Test (DFT) solutions for SoC/ASIC digital designs.
• Perform scan chain insertion, compression scan technologies, and memory built-in self-test (MBIST).
• Generate automatic test patterns (ATPG) to achieve design test coverage goals.
• Debug and analyze failures to improve fault coverage.
• Verify ATPG testbenches and debug root cause of simulation mis-compares.
• Work with stakeholders across cross-functional teams (Architecture, Design, Internal and External Customers).

Requirements

• US citizenship required.
• 10-20 years of professional experience in SoC/ASIC Digital Design with a focus on Design for Test (DFT).
• Intimate knowledge of DFT insertion flows, basic scan chain insertion, compression scan insertion, and MBIST.
• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals.
• Working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687.
• Strong problem-solving skills, discipline, thoroughness, and methodical approach in solving problems.

Nice to have

• Knowledge of timing analysis and equivalency checks.
• Prior experience with hirify.global tools and flows.

Culture & Benefits

• Opportunity to make an impact on the world of technology.
• Work in a collaborative team environment.
• Be part of a self-driven and committed team in a fast-paced project environment.