Sr DFT Engineer

TL;DR

Sr. DFT Engineer: Developing, maintaining, and supporting DFT methodologies and flows for integrated, RTL-centric environments across company IPs, chiplets, and SoC designs with an accent on automated verification, scan insertion, and ATPG retargeting. Focus on architecting end-to-end verification solutions, building automated QoR checks, and integrating custom DFT logic for complex SoCs and CoWoS designs.

Location: Hybrid work environment in Toronto, Canada

Company

hirify.global enables critical data communication for data centers, networking, storage, AI, 5G, and autonomous vehicles.

What you will do

• Develop, maintain, and support central DFT methodologies and flows across all company projects.
• Architect integrated, RTL-centric "shift left" DFT environments for IPs, chiplets, and SoCs.
• Develop automated verification test benches and sequences for DFT IP, including end-to-end solutions.
• Build IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures.
• Define static timing constraints and create flows for robust timing checks.
• Lead and train DFT engineers to achieve company roadmap objectives.

Requirements

• Bachelor's degree in Engineering Science, Electrical and Computer Engineering, or Computer Science.
• 5+ years of experience in complex SoC designs (RTL, DFT, or FE capacity).
• Vast experience with DFT EDA tools from Tessent, SNPS, and Cadence.
• Strong knowledge of Verilog/VHDL and SystemVerilog.
• Extensive experience with main DFT standards (JTAG, iJTAG) and BIST techniques (memory, logic, interconnect BISTs).
• Experience in SoC and IP/Block level scan insertion, ATPG, and custom DFT logic integration for complex SoCs/CoWoS.

Culture & Benefits

• Comprehensive benefits package including Health Insurance, Retirement Savings, and Paid Time Off.
• Hybrid work environment.
• Commitment to diversity and inclusivity.
• Equal opportunity employer offering accommodation for disabilities.