Director Post-Si Electrical Validation Engineering (SerDes/PCIe)

Location: San Jose, California, United States

Salary: $210,000–$275,000 depending on experience, level, and business need; discretionary bonus, incentives, and benefits may also be available.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

• Lead ASIC electrical-level PHY validation strategy from product definition and architecture through PCB and test-fixture development, bring-up, qualification, production release, and post-production support.
• Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed ASIC and PHY IP.
• Direct power-on, silicon and PCB debug, PVT characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions.
• Validate NRZ and PAM4 SerDes protocols, including PCIe Gen 3 and above, and apply signal integrity, power integrity, coding, and laboratory expertise to resolve hardware risks.
• Partner with ASIC, firmware, systems, mechanical, thermal, manufacturing, quality, compliance, and customer engineering teams, while collaborating with external test-equipment and manufacturing vendors.
• Build and mentor a high-performing engineering team, improve post-silicon methodologies, and drive reusable validation practices across connectivity and memory products.

Requirements

• Bachelor’s degree in Electrical Engineering or a related technical field.
• 12–15+ years of relevant experience, consistent with the standardized Director level.
• Technical management experience leading design, validation, product, or system engineering teams.
• Experience with high-speed SerDes PHY validation across PVT conditions and taking products from concept through validation planning, validation, production release, and post-production support.
• Strong background in high-speed SerDes IP validation and PHY tuning, signal and power integrity, and automation using high-speed oscilloscopes, BERTs, VNAs, and similar laboratory equipment.
• Strong cross-functional collaboration, technical communication, prioritization, and independent problem-solving skills.
• Entrepreneurial, open-minded, customer-focused behavior and a can-do attitude.

Nice to have

• Experience leading SoC debug and development for PCIe 5, PCIe 6, or PAM4 802.3 Ethernet interfaces.
• Knowledge of high-speed PHY blocks including PLLs, DFE, Tx EQ, FFE, and CDR, as well as PAM4 signaling.
• Strong Python scripting and object-oriented programming skills, with basic Git-based DevOps knowledge.
• Experience developing Python-based bench automation focused on execution efficiency, repeatability, and data analysis.
• Proficiency with BERTs, oscilloscopes, VNAs, and other high-speed laboratory equipment.
• Startup experience and a proactive, hands-on, customer-focused approach to solving complex problems.

Culture & Benefits

• Hands-on leadership role in a fast-moving hardware engineering environment.
• Work includes direct customer engagement and collaboration across internal engineering and external vendor teams.
• Bonus, incentives, and benefits may be available in addition to base salary.
• Applications are encouraged from candidates with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.