Senior Principal Engineer, Device Design (Semiconductor)

Location: Hybrid role based at an assigned hirify.global site in Hillsboro, Oregon; Santa Clara, California; or Phoenix, Arizona, United States.

Annual salary range: $265,480–$374,800 USD.

Company

hirify.global is transforming from an integrated device manufacturer into a global foundry service provider, delivering semiconductor manufacturing capabilities to external customers.

What you will do

• Lead the architecture and technical definition of base and derivative semiconductor technologies, including transistors, interconnects, and design rules.
• Guide customized technology development for high-performance logic, low-power, memory, analog, and mixed-signal applications.
• Partner with customers, product design teams, Process Integration, Process Module, Device Physics, Yield Engineering, and Product Design groups.
• Set device and interconnect performance targets and govern silicon-to-simulation readiness, model readiness, and manufacturing feasibility.
• Direct design rule validation and waiver governance while balancing manufacturing compliance, yield, and product design flexibility.
• Evaluate E-test and yield data using statistical methods and provide technical mentorship and industry leadership.

Requirements

• Progressive semiconductor industry experience focused on CMOS device physics, device design, and semiconductor technology development.
• Technical leadership experience leading cross-functional teams to define, develop, and deliver advanced semiconductor technologies and design rules into high-volume manufacturing.
• Deep proficiency in design rule development, validation, and waiver management, including understanding of layout constraints and product yield.
• Expertise in statistical data analysis, Design of Experiments, and interpretation of test chip, E-test, and yield trends.
• Master’s degree in Electrical Engineering, Physics, Material Science, or a related field; PhD preferred.
• 15+ years of relevant semiconductor device and technology development experience.
• Successful completion of an extended background investigation is required, including education, SEC sanctions, and additional criminal and civil checks subject to applicable country law.

Nice to have

• Architectural experience with advanced-node transistor design and scaling, including customization for low-power, analog, mixed-signal, and memory technologies.
• Familiarity with physical verification flows, Design Rule Checker development, and mask generation concepts.
• Extensive high-volume manufacturing experience with statistical process control and yield monitoring.
• Exceptional written and verbal communication skills, including influencing executive stakeholders and guiding partners through technical trade-offs.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned hirify.global location with off-site work.
• Competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
• Full-time employment as an experienced hire on Shift 1 in the United States.
• Position of Trust subject to the required background investigation.