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5 дней назад

Senior ASIC Design Verification Engineer (Slingshot)

147 000 - 279 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
c1
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Design Verification Engineer (Slingshot) (ASIC/SystemVerilog/UVM): Developing pre-silicon verification for switch and NIC ASICs used in high-performance computing and AI interconnects with an accent on testbench architecture, coverage closure, and verification methodology. Focus on building block and integration-level scoreboards and checkers, triaging complex regression failures, and applying automation and agentic AI tools to improve verification quality.

Location: Hybrid, with an average requirement of 2 days per week from an HPE office in Chippewa Falls, Wisconsin; Bloomington, Minnesota; or Fort Collins, Colorado, United States

Salary: $147,000–$279,000 annual base salary in Colorado; $140,000–$321,000 annual base salary in Minnesota and Wisconsin. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud company developing infrastructure and solutions that connect, protect, analyze, and manage data and applications.

What you will do

  • Own significant verification scope for switch and NIC ASICs supporting future generations of the HPE Slingshot interconnect for HPC and AI systems.
  • Follow and help define design verification methodology, develop test plans and testbenches, and participate in coverage closure and sign-off reviews.
  • Build SystemVerilog and UVM testbench components, including bus functional models, scoreboards, and functional checkers for block and integration-level verification.
  • Write and analyze functional coverage, triage regression failures, identify logic bugs, and drive bug closure.
  • Apply scripting, automation, and AI-assisted or agentic tools to improve verification speed and quality.
  • Mentor less experienced engineers, influence technical direction, and contribute to VLSI innovation and technical-leader selection.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
  • 10+ years of experience in VLSI design, verification, or implementation.
  • Expert knowledge of SystemVerilog and OVM or UVM methodologies.
  • Expert knowledge of programming and scripting languages, hardware description languages, EDA, and/or FPGA tools.
  • Expert analytical and problem-solving skills.
  • Ability to excel in a distributed team environment.
  • Executive-level written and verbal communication skills and mastery in English.

Nice to have

  • Experience verifying high-speed networking, switching, or NIC ASICs.
  • Experience with agentic AI coding tools and workflows applied to verification.
  • Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
  • Experience working as part of a geographically distributed team.

Culture & Benefits

  • Hybrid work arrangement with regular office collaboration.
  • Health and wellbeing benefits supporting physical, financial, and emotional wellbeing for employees and their loved ones.
  • Personal and professional development programs supporting career growth and movement across divisions.
  • Inclusive workplace that values varied backgrounds and individual uniqueness.

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