linuxci cdverificationasicsocsystemveriloguvmsvaverification ip
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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У роли понятный фокус на senior-верификации и работе со сложными ASIC/SoC, но из-за консалтинговой модели и обязательного присутствия в офисе стоит уточнить конкретный проект и повседневные условия.
?Работа через консалтинг
Актуальные технологии
Понятные задачи
Варианты развития
?Работа в офисе
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior ASIC Verification Engineer (SystemVerilog/UVM): Developing and improving advanced ASIC and SoC verification environments for high-performance telecommunications and connectivity hardware with an accent on testbench architecture, Verification IP, assertions, and coverage-driven verification. Focus on designing verification environments from scratch, closing functional and code coverage gaps, and collaborating on complex digital systems in an international R&D environment.
Location: hirify.global South – Malmö and the surrounding region; onsite
Company
hirify.global is an engineering consultancy providing assignments across technologies, customers, and industries, with a focus on professional development, collaboration, and long-term employee support.
What you will do
Develop advanced ASIC and SoC verification environments using SystemVerilog and UVM.
Design and implement testbenches from scratch, including drivers, monitors, scoreboards, and sequences.
Develop, integrate, and maintain Verification IPs and SystemVerilog Assertions.
Build functional and code coverage strategies, identify verification gaps, and drive coverage closure.
Maintain and improve verification environments as designs evolve.
Collaborate with multidisciplinary engineering teams and contribute to verification methodologies and best practices.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
At least five years of relevant experience, preferably with a strong focus on ASIC/SoC verification.
Excellent knowledge of SystemVerilog and UVM.
Hands-on experience developing verification testbenches and environments from scratch.
Experience developing and integrating Verification IPs.
Understanding of assertions, functional coverage, code coverage, and coverage-driven verification.
Solid understanding of digital design and modern verification methodologies.
Experience working in Linux-based development environments.
Strong communication skills and ability to collaborate in international, cross-functional engineering teams.
Nice to have
ASIC verification experience in telecommunications, networking, or high-speed interfaces.
Experience with regression testing, automation, and CI environments.
Experience analyzing verification metrics and improving verification efficiency.
Previous experience mentoring engineers or contributing to technical team development.
Experience in large-scale, international R&D organizations.
Culture & Benefits
Permanent, full-time employment.
Opportunities to deepen technical expertise, take on technical responsibility, or grow into leadership.
Supportive leadership, open culture, knowledge sharing, and social activities.
Pension contributions, comprehensive insurance coverage, professional development opportunities, and employee benefits.
Start date planned for early 2027 or spring 2027, depending on availability and agreement.
Hiring process
Applications and interviews are handled continuously.
Applications are not accepted by email.
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