Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$200к-350к/год
$190к$230кмедиана$280к
По похожим ролям (49) ~ $230к/год
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Крутая вакансия
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Чёткая зона ответственности на сложном проекте в сфере AI-чипов делает вакансию сильной, хотя ранняя стадия стартапа и работа только в офисе добавляют неопределённости.
Риски стартапа
AI-железо
Своя зона ответственности
Современный подход
Поддержка с визой
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior Design Verification Engineer (AI): Owning verification strategy and functional closure for complex AI accelerator IP, subsystems, and full-chip designs with an accent on UVM testbench architecture, SoC-level testing, and emulation. Focus on debugging complex hardware/software interactions, identifying verification gaps, and delivering end-to-end pre-silicon verification results.
Location: Mountain View, California, United States — onsite
Salary: $200,000–$350,000 base plus equity
Company
hirify.global is working with an early-stage AI compute company developing a full-stack platform based on system-on-wafer architecture and advanced 3D integration to reduce power, latency, and infrastructure costs in AI clusters.
What you will do
Own a verification domain from specification analysis and verification planning through debug and functional closure.
Develop end-to-end verification strategies across IP, SoC-level testing, and emulation.
Build and maintain UVM testbench architecture for complex AI accelerator designs.
Collaborate with hardware and software engineers to understand system behavior, identify verification gaps, and resolve failures.
Influence verification strategy, testbench design, tooling, and AI-assisted verification and emulation methods.
Requirements
At least five years of pre-silicon verification experience, including ownership of complex IP, subsystems, or SoCs from planning through functional closure.
Strong experience in one or more of block or subsystem verification, CPU subsystem and IP integration, full-chip verification, emulation, DMA/NoC, or multi-SoC and die-to-die protocols.
Strong command of UVM methodology and testbench architecture.
Experience debugging complex designs and delivering end-to-end verification results.
Ability to interpret specifications from both hardware and software perspectives.
Nice to have
RISC-V experience.
Formal verification experience.
Experience with Palladium, Veloce, or similar emulation platforms.
Post-silicon bring-up experience.
Culture & Benefits
Technical ownership of a substantial verification domain within a new AI computing platform.
Direct collaboration with engineers shaping the hardware and software architecture.
Opportunity to influence verification strategy, testbench design, and tooling within a growing team.
Visa sponsorship and immigration support are available for qualified candidates.
Close connection between verification work and accelerator silicon delivery.
Hiring process
Interested candidates are invited to start a conversation.
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