2027 Internship - Formal Verification Engineer

Location: Austin, Texas; hybrid schedule with at least 2 days in the office and interns potentially working onsite up to 5 days per week. Interns must live within commuting distance or be willing to relocate to the United States before starting.

Company

hirify.global develops mixed-signal processing solutions for consumer brands and maintains a culture focused on inclusion, fairness, community engagement, and employee experience.

What you will do

• Support and improve formal verification methodology practices.
• Develop test plans and verification methodologies for microarchitecture and digital designs.
• Perform failure analysis, resolution, coverage analysis, and coverage population.
• Implement and improve functional and formal verification.

Requirements

• Currently enrolled in a Master's or PhD program in Electrical or Computer Engineering and available for full-time employment during the internship.
• Knowledge of designing and implementing verification environments for module-level designs.
• Proficiency in SystemVerilog.
• Familiarity with scripting languages such as Python, Perl, TCL, and Bash.
• Experience or knowledge of UVM or equivalent methodologies.
• Knowledge of formal property languages such as SVA and property-based model-checking.
• Knowledge of signal processing and analog or digital design fundamentals.
• Excellent communication skills and a collaborative approach to working with team members.
• Ability to access technical data without requiring an export license; hirify.global cannot sponsor or obtain export licenses for this role.

Culture & Benefits

• Hybrid work with a standard schedule of at least 2 days in the office.
• Interns may work onsite up to 5 days per week based on business needs and team preference.
• Inclusive and fair work environment with meaningful community engagement.
• Career growth opportunity within a mixed-signal processing engineering organization.