Senior Principal Validation Engineer (VCSEL Optical Interconnect)

Location: Pavia, Italy

Expected base pay: €73,300–€97,700 per annum

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, communication infrastructure, and optical interconnect applications.

What you will do

• Set the validation, test-platform, bench, instrumentation, and measurement strategy across labs in Italy, Vietnam, Canada, and the US.
• Design and develop electrical and optical VCSEL interconnect benches, including architecture, instrument qualification, calibration, automation, and cross-site correlation.
• Design evaluation boards, characterization boards, PCBs, test fixtures, and optical/electrical adapters from requirements and schematics through SI/PI, layout, fabrication, assembly, and bring-up.
• Develop optical-link and high-speed electrical measurement methods covering power, spectrum, eye and waveform analysis, BER, noise, jitter, and link margin.
• Bring up, debug, characterize, and validate electro-optical chiplets and products from first silicon through product tape-out while working with silicon, analog, DSP, firmware, optics, packaging, and PCB teams.
• Automate instruments and data flows in Python, document test plans and results, and hire, coach, and mentor engineers while serving as a technical authority for vendors and cross-functional leadership.

Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Physics, Optical Engineering, or a related field, with 15+ years of related experience for a Bachelor's degree or 10+ years for a Master's/PhD.
• Recognized expert-level experience with high-speed electrical laboratory measurements using real-time and sampling oscilloscopes, BERT, VNA/TDR, AWG, spectrum analyzers, and solid laboratory techniques.
• Recognized expert-level experience with optical measurements using optical power meters, optical spectrum analyzers, optical/high-speed photoreceivers, fiber handling, and optical alignment.
• Experience automating benches in Python through SCPI/VISA/GPIB and analyzing data with Python, MATLAB, JMP, or R.
• Working knowledge of high-speed board design, including schematics and layouts, SI/PI, transmission-line and EM fundamentals, PCB materials, fabrication, and assembly; experience with OrCAD/Allegro or equivalent tools.
• Strong fundamentals in communication systems and analog and digital circuits.
• Proven technical leadership defining strategy, building and leading multi-site teams, and influencing multifunctional organizations.
• Strong troubleshooting and root-cause analysis skills.
• Fluent English required, with readiness to work with remote teams across Italy, Vietnam, Canada, and the US.
• Applicants must be eligible to access export-controlled technology and software; an export license review may be required before employment.

Nice to have

• Experience with VCSELs, photodetectors, optical modules, or electro-optical interconnect characterization.
• Experience with chiplet or die-to-die interfaces and qualification of external optics suppliers.
• Knowledge of DSP communication theory and data-networking physical-layer specifications.
• Experience building a laboratory capability or validation organization from scratch.

Culture & Benefits

• Employment is classified as Quadro under the applicable Italian collective labor agreement.
• Eligible for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Benefits support collaboration, transparency, inclusion, and professional growth.
• hirify.global is committed to equal employment opportunity and encourages applications from qualified candidates with disabilities and protected categories under Italian Law 68/99.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are prohibited during interviews; unauthorized use results in disqualification.

Hiring process

• Interviews assess individual experience, thought process, and communication skills in real time.
• Do not use AI tools to record, assist with, or enhance interview responses unless instructed by the interviewer.