pythonsocverilogdftcdcsystemverilogedaformal verificationmcudigital ic design
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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€61к-84к/год
€50к€61кмедиана€68к
По похожим ролям (43) ~ €61к/год
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Чётко очерченная роль ведущего инженера в крупной полупроводниковой компании сочетает полный цикл разработки SoC, техническое лидерство и работу над продуктами для AI на периферии.
Актуальный стек
Широкая зона ответственности
AI на периферии
Крупный разработчик чипов
Мэтч & Сопровод
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Текст:
Hirify AI/Оригинал
TL;DR
Principal Digital Design Engineer (MCU): Leading full digital IC design flows for complex MCU SoCs with an accent on RTL design, synthesis, verification, DFT, and power-performance-area optimization. Focus on defining digital architectures, debugging post-silicon issues, integrating analog and software interfaces, and mentoring junior engineers.
Location: Catania, Italy
Salary: €61,000–€83,900 gross annual base salary
Company
hirify.global develops industrial and IoT edge-processing solutions, including microcontrollers and high-performance processors for automation and embedded applications.
What you will do
Lead the full digital IC design flow for complex MCU SoCs, from specification and architecture through RTL coding, synthesis, static timing analysis, formal verification, and power analysis.
Contribute to design-for-testability implementation and verification, and develop architectures and methodologies meeting performance, power, and area targets.
Collaborate with analog, mixed-signal, and software teams on interfaces, integration, and system performance.
Document specifications, test plans, and design reviews; contribute to design-process improvement and industry best practices.
Mentor junior engineers, provide technical guidance, and lead technical discussions.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
At least 10 years of experience in digital IC design, with successfully completed projects.
Expertise in Verilog and SystemVerilog for RTL design and verification.
Experience with industry-standard EDA tools for synthesis, STA, formal verification, and simulation, including tools such as Synopsys Design Compiler, Cadence Genus, PrimeTime, Synopsys Formality, VCS, or QuestaSim.
Strong understanding of digital design principles, clock-domain crossing issues, power integrity, and low-power design techniques.
Experience with Python, Perl, or Tcl scripting for automation and design-flow optimization.
Familiarity with mixed-signal integration challenges and verification methodologies.
Excellent problem-solving, analytical, debugging, communication, and interpersonal skills.
Ability to take initiative, work independently, collaborate effectively, and lead technical discussions.
Culture & Benefits
Full-time role in a fast-paced MCU SoC R&D team in Catania.
Cross-functional collaboration across analog, digital design, architecture, verification, DFT, physical design, and software.
Gross annual base salary governed by the applicable Metalmeccanica Industria National Collective Labour Agreement.
Potential annual incentive opportunities, equity, and a competitive benefits package.
Equal-pay and transparent remuneration practices.
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