pythonc++asicdigital designdspverilogsystemverilogmixed signalaudio signal processingdigital verification
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Чётко описанная senior-роль охватывает полный цикл разработки ASIC для edge AI, но требование от 10 лет опыта и работа только на месте сужают круг тех, кому подойдёт эта возможность.
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Только офисAI на устройствахСовременный стекПолный цикл ASIC
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Текст:
Hirify AI/Оригинал
TL;DR
Sr. Staff Digital Design Engineer (ASIC/AI): Designing, implementing, and verifying DSP algorithms, digital control logic, and audio-processing interfaces for ASICs with an accent on RTL design, mixed-signal integration, and complete digital ASIC flow ownership. Focus on architecting filters and decimators, building verification environments, validating performance, and supporting silicon bring-up and failure analysis.
Location: On-site in Rapperswil-Jona, St. Gallen, Switzerland
Company
hirify.global develops ultra-low-power semiconductor and software solutions for edge AI speech, audio, sensor, and vision applications.
What you will do
Design, implement, and verify DSP algorithms, interfaces, and protocols for ASIC audio processing.
Implement and verify digital control logic supporting MEMS microphones.
Contribute across the digital ASIC flow, including specification, modeling, implementation, verification, synthesis, and silicon bring-up.
Perform design validation and performance testing.
Document blocks and systems and support complex failure analysis for production ramp-up.
Requirements
Advanced degree in electronics engineering.
10+ years of experience developing digital blocks or systems for high-performance mixed-signal integrated circuits in consumer or industrial R&D.
Strong understanding of digital signal processing, including Z-transform, frequency response, SNR, and THD.
Experience architecting and implementing DSP algorithms such as filters and decimators using MATLAB Simulink.
Experience with RTL implementation of DSP algorithms using Verilog or SystemVerilog.
Experience implementing RTL test benches and digital verification methods.
Deep understanding of analog and mixed-signal blocks, including op-amps, LDOs, ADCs, and DACs.
Programming or scripting experience with Python, C/C++, or Perl.
Task-centered, self-driven, persistent, and team-oriented approach.
Nice to have
Audio signal-processing experience, including beamforming, echo cancellers, or adaptive filters.
Experience with energy-management, speech-processing, and audio-processing algorithms, including noise cancellation, acoustic echo cancellation, signal enhancement, and microphone or speaker arrays.
Culture & Benefits
Full-time, on-site position within the Hardware department.
Opportunity to work on edge AI semiconductor solutions deployed across consumer and industrial applications.
Compensation is determined based on experience, skills, cost of living in the assigned location, schedule, and comparable internal salaries.
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