Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$200к-350к/год
$160к$200кмедиана$230к
По похожим ролям (48) ~ $200к/год
На СНГ рынке: $2.5к/мес ($1.9к - $3к)
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Крутая вакансия
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У роли четкая узкая специализация и важная позиция в амбициозной AI-платформе, хотя ранняя стадия компании означает больше неопределенности, чем у зрелого работодателя.
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Риски стартапаПередовая упаковкаЧеткая зона ответственностиСовременные технологии
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Advanced Package Layout Engineer (AI): Owning multi-die 2.5D and 3D package layout for a system-on-wafer AI computing platform with an accent on substrate and interposer routing, HBM-class channels, and high-current power delivery. Focus on closing package DRC/LVS, coordinating silicon and board interfaces, developing AI-assisted layout tools, and taking complex designs through manufacturing release.
Location: Mountain View, California, United States — onsite.
Salary: $200,000–$350,000 per year.
Company
Early-stage AI compute company developing a full-stack platform based on system-on-wafer architecture and advanced 3D integration to reduce power, latency, and infrastructure costs in AI clusters.
What you will do
Own package substrate and interposer layout from stackup definition, bump and ball maps, RDL, and escape routing through manufacturing release and tape-out.
Plan high-density routing and HBM-class channels alongside power and ground structures for accelerator rails carrying hundreds of amps.
Collaborate with physical design engineers on die floorplans and bump placement and with PCB layout engineers on the package-to-board interface.
Close package DRC/LVS and netlist verification against substrate supplier and OSAT design rules, including rule negotiation where required.
Work with architecture, SI/PI, thermo-mechanical, and manufacturing partners to resolve trade-offs and achieve package sign-off.
Develop and use AI-assisted tools to accelerate package layout, routing, and sign-off.
Requirements
At least eight years of package layout experience on high-performance designs, including multi-die 2.5D and 3D packages.
Strong practical experience with advanced packaging technologies such as CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies.
Deep expertise in substrate and interposer routing, high-density escape, stackup design, and via structures.
Experience designing power and ground planes for high-current accelerator rails.
Hands-on experience with Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Package Designer, or equivalent tools.
Practical ownership of package DRC/LVS, netlist verification, and design release.
Culture & Benefits
Broad technical ownership of a critical part of an AI computing platform.
Close collaboration with silicon, board, architecture, signal integrity, power integrity, thermo-mechanical, and manufacturing engineers.
Responsibility for package releases used by manufacturing partners.
Medical, dental, and vision insurance.
401(k) plan.
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