pythondebuggingfpgasystemveriloguvmdesign verificationtclhdlconstrained random verificationcoverage closure
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Обязанности senior-инженера по верификации четко очерчены и охватывают полный цикл UVM-проверок в известной продуктовой компании; зарплата и конкретные условия развития не указаны.
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Hirify AI/Оригинал
TL;DR
Senior Design Verification Engineer (SystemVerilog/UVM): Developing and validating scalable pre-silicon verification environments for complex IPs with an accent on constrained-random testing, coverage closure, and verification sign-off. Focus on creating UVM test infrastructure, debugging design failures, and collaborating across design, architecture, system validation, and application teams.
Location: Penang, Malaysia
Employment type: Full time
Company
hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.
What you will do
Develop and review comprehensive test plans based on design specifications.
Develop and maintain scalable UVM-based constrained-random verification environments for complex IPs.
Create test cases, sequences, scoreboards, checkers, and assertions, and drive verification from planning through coverage closure and sign-off.
Analyze failures and perform root-cause debugging of design and verification issues.
Collaborate with design, architecture, system validation, and application teams to resolve functional and performance issues and customer escapes.
Contribute to verification methodology improvements, automation initiatives, and team best practices.
Requirements
Minimum 5+ years of hands-on Design Verification experience using SystemVerilog and UVM.
Good understanding of the verification process from test planning through coverage closure and sign-off.
Hands-on experience with SystemVerilog and UVM verification methodologies.
Experience developing constrained-random verification environments for complex digital designs.
Good understanding of HDL, including Verilog and SystemVerilog.
Proficiency in at least one scripting or programming language such as Python, Tcl, Perl, or C/C++.
Strong debugging, analytical, problem-solving, communication, and teamwork skills in a cross-functional and geographically distributed environment.
BS, MS, or PhD in Electrical Engineering, Electronics Engineering, or Computer Engineering.
Independent, self-motivated, and capable of delivering results in a dynamic environment with evolving priorities.
Successful background and reference checks and satisfactory proof of the right to work in Malaysia are required.
Nice to have
Experience designing with FPGA.
Experience with high-speed interface protocols such as Ethernet, PCIe, CPRI, JESD204B/C, or USB.
Experience with memory technologies or components such as DRAM, SRAM, Flash, or DMA.
Experience with interconnects such as AMBA AXI, AHB, or APB.
Experience with peripherals such as SPI, I2C, or I3C.
Culture & Benefits
Work in an international, results-oriented, team-first environment.
Collaborate with globally distributed engineering, design, manufacturing, sales, marketing, and support teams.
Opportunities to contribute, learn, and grow within the R&D organization.
Comprehensive compensation and benefits programs are provided.
Applications are welcome from all qualified candidates, with a stated commitment to workplace diversity.
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