SoC Physical Designer

Location: Tianjin (Teda), China

Company

hirify.global develops semiconductor products and advanced SoC technologies.

What you will do

• Support SoC and subsystem physical design implementation from netlist to GDSII.
• Participate in floorplanning, power planning, placement, clock tree synthesis, routing, and chip finishing.
• Perform timing, power, signal integrity, and physical verification analysis.
• Debug implementation issues and drive convergence toward performance, power, area, and cost targets.
• Collaborate with RTL Design, DFT, Verification, IP, Package, and Technology teams.
• Support silicon bring-up, design reviews, tapeout, and continuous improvement of backend methodologies and flows.

Requirements

• Master's degree, graduating in 2027, in Microelectronics, Integrated Circuit Design, Electronic Engineering, Computer Engineering, Automation, or a related discipline.
• Basic knowledge of VLSI design flow and semiconductor fundamentals.
• Familiarity with Linux/Unix environments.
• Programming experience in Python, Tcl, Perl, Shell, or C/C++.
• Strong analytical, problem-solving, communication, and teamwork skills.
• Fluent written and spoken English required.

Nice to have

• Coursework or project experience in ASIC/SoC design, physical design, timing analysis, DFT, or digital IC design.
• Hands-on experience with Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, Tempus, or Calibre.
• Experience applying machine learning or AI to semiconductor design.
• Publications, competitions, or research projects related to EDA or IC design.

Culture & Benefits

• Full-time role involving cross-functional collaboration across design and technology teams.
• Opportunity to contribute to backend methodology, automation, and engineering productivity improvements.