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Senior Analog IC Layout Engineer - MCU

50 600 - 69 600€
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
c1
Страна
Italy
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Мэтч & Сопровод

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Описание вакансии

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TL;DR
Senior Analog IC Layout Engineer - MCU (Analog/Mixed-Signal IC Layout): Driving physical implementation of complex analog, mixed-signal, and custom digital blocks from floorplanning through tape-out with an accent on matching, routing, physical verification, and advanced FinFET technologies. Focus on solving complex implementation issues, managing parasitics and reliability constraints, and guiding layout execution toward high-quality silicon delivery.

Location: Catania, Italy

Salary: €50,600–€69,600 gross annual base salary

Company

hirify.global develops semiconductor technologies and products, including complex analog, mixed-signal, and custom integrated circuits.

What you will do

  • Lead physical implementation of complex analog, mixed-signal, and custom digital blocks from floorplanning through tape-out.
  • Develop device matching, shielding, noise isolation, routing, power distribution, and layout optimization strategies.
  • Perform and review DRC, LVS, ERC, EM/IR, latch-up, density, and reliability verification activities.
  • Collaborate with design, verification, technology, and product engineering teams to resolve implementation challenges.
  • Support advanced-node technologies, including FinFET processes, and improve layout methodologies and best practices.
  • Estimate layout effort, manage project risks and schedules, and mentor junior engineers and contractors.

Requirements

  • BSEE or MSEE and approximately 8–12+ years of custom analog or mixed-signal layout experience in deep sub-micron CMOS.
  • Expertise in Cadence Virtuoso XL, floorplanning, constraint-driven layout, and PVS DRC/LVS/ERC.
  • Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, DFM, ESD, power distribution, and multiple voltage domains.
  • Experience leading analog-on-top and digital-on-top chip layouts and working with PLL, OSC, ADC, DAC, LDO, bandgap, and high-speed interface circuits.
  • Proven tape-out experience, strong technical judgment, and cross-functional leadership skills.
  • Fluent English is required.

Nice to have

  • SKILL or Perl scripting experience.

Culture & Benefits

  • Full-time position covered by the applicable Metalmeccanica Industria National Collective Labour Agreement.
  • Fair, consistent, and transparent remuneration practices.
  • Potential annual incentive opportunities and equity, where applicable.
  • Competitive benefits package.

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