Analog IC Design Engineer, Intern (AI)

Location: Onsite at the office in Pavia, Italy

Expected base pay: €21,250–€28,750 annual rate

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

• Design integrated circuits for electrical and electro-optical interfaces operating at 100+ Gb/s.
• Use advanced 3nm FinFET and 2nm GAAFET technology nodes.
• Learn and use CAD tools, primarily Cadence, to design and simulate high-performance analog circuits.
• Develop advanced analog and high-speed layout skills.
• Collaborate with the analog engineering team to deliver effective outcomes.

Requirements

• Bachelor’s degree in Electronics Engineering, or current enrollment in a Master’s or PhD thesis program.
• Academic knowledge of CMOS analog design and understanding of CMOS processes and fabrication.
• Basic knowledge of IC layout.
• Proficiency in spoken and written Italian and English at B2 level or higher.
• Strong written and verbal communication skills and the ability to work effectively in a team.

Nice to have

• Basic knowledge of RF design techniques.

Culture & Benefits

• Six-month full-time contract suitable for sponsorship of an industrial Master Thesis.
• Opportunities to learn multiple IC design engineering skills and tools.
• Collaborative, transparent, and inclusive work environment.
• Professional development resources and competitive benefits.