Principal FW/SW Engineer (Ethernet)

Location: Remote in Toronto or Ottawa, Ontario, Canada. Occasional travel to the San Jose headquarters, approximately twice per year, is required for chip bring-up and project coordination.

Salary: CAD $184,500–$205,000, depending on experience, level, and business need. The role may also be eligible for discretionary bonuses, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and software technologies.

What you will do

• Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs.
• Design adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and telemetry functionality.
• Debug Ethernet configurations and failure modes across PHY, SERDES, FEC/PCS, MAC, retimer, and gearbox components.
• Investigate register accesses, SDK behavior, link state machines, telemetry, logs, and real-hardware measurements to identify root causes.
• Develop validation plans and automated characterization flows from pre-silicon work through production deployment.
• Set technical direction, lead architecture and code reviews, resolve complex integration issues, and mentor engineers across firmware, silicon, analog, systems, validation, and applications.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
• 8–12 years of experience developing embedded firmware or software for resource-constrained systems, with ownership from architecture through production.
• Strong embedded C/C++ skills and deep knowledge of microcontrollers, memory-mapped peripherals, interrupt handling, and bare-metal firmware.
• Hands-on experience with Ethernet or high-speed connectivity devices such as Layer 1 PHYs, SERDES, retimers, gearboxes, NICs, or switches.
• Experience with physical-layer behavior, link state machines, register-level debugging, feedback systems, adaptive algorithms, calibration, or mixed-signal tuning.
• Proficiency with Microsoft-based development environments and Linux command-line tools, including GCC or Clang, Make, Bash, GDB, and Git.

Nice to have

• Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
• Python experience for test automation, debug tooling, data analysis, or lab workflows, plus Jenkins and CI/CD experience.
• Experience with mixed-signal systems, analog signal paths, ADC/DAC interfaces, CTLE/DFE equalization, CDR/PLL circuits, or thermal control.
• Experience with retimer or gearbox firmware, SDK/API development, optical modules, high-speed copper connectivity, Ethernet PHY subsystems, FEC, PMA, or signal-integrity analysis.
• Experience with oscilloscopes, BERTs, logic analyzers, FPGA emulation, pre-silicon validation, RTOS, device drivers, mentoring, or recruiting.

Culture & Benefits

• Cross-functional collaboration with silicon, analog, systems, validation, applications, and platform teams.
• Opportunity to influence architecture and technical direction for production connectivity products.
• Occasional travel to San Jose for chip bring-up and project coordination.
• Potential eligibility for discretionary bonuses, incentives, and benefits.
• People-management or senior technical-lead growth paths may become available as the organization expands.