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5 дней назад

DFT Intern

Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
Singapore
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
DFT Intern (SoC/Scan/MBIST): Supporting scan and MBIST implementation and verification for ultra-low-power SoC designs with an accent on test coverage, test quality, and low-power DFT methodologies. Focus on analyzing DFT rule-checking results, debugging timing and testability issues, and developing Tcl, Python, and Shell automation for engineering workflows.

Location: Singapore

Company

hirify.global develops ultra-low-power semiconductor solutions for AI edge, wearable, medical device, IoT, and other intelligent applications.

What you will do

  • Support low-power DFT implementation and verification for SoC designs.
  • Assist with scan insertion, scan-chain verification, and MBIST insertion for embedded memories.
  • Analyze DFT rule-checking results and help resolve design, testability, coverage, and timing issues.
  • Support test-coverage analysis and identify opportunities to improve coverage and test quality.
  • Develop and maintain Tcl, Python, and Shell scripts to automate recurring engineering tasks.
  • Document methodologies and results, present progress, and collaborate with RTL, DFT, DV, and physical design engineers.

Requirements

  • Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • Coursework in digital logic, VLSI or ASIC design, and CMOS circuits; computer architecture is preferred.
  • Familiarity with Verilog, SystemVerilog, or VHDL and digital design concepts including timing, clocking, reset, and pipelining.
  • Comfort working in a Linux or UNIX environment.
  • Strong analytical, debugging, problem-solving, communication, and collaboration skills.

Nice to have

  • Experience with EDA tools for scan insertion, ATPG, MBIST, memory repair, ASIC design, or synthesis.
  • Understanding of scan, ATPG, MBIST, fault coverage, memory repair, and fault models such as stuck-at, transition, bridging, and memory faults.
  • Understanding of low-power concepts including multiple power domains, retention, and clock gating.
  • Scripting experience in Tcl, Python, or Shell for flow automation.

Culture & Benefits

  • Hands-on experience with industry-standard DFT tools and methodologies.
  • Opportunity to work alongside experienced engineers on edge AI products.
  • Cross-functional collaboration across RTL, DFT, design verification, and physical design.
  • Mentorship and exposure to complex semiconductor development work.

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