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6 дней назад

Principal Formal Verification Engineer (AI Hardware)

250 000 - 350 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal Formal Verification Engineer (AI Hardware): Owning block- and SoC-level formal verification for AI accelerator silicon, developing SystemVerilog Assertions and verification environments with an accent on proof convergence, microarchitectural correctness, and AI-assisted workflows. Focus on debugging proof failures, building verification infrastructure, and collaborating with RTL, architecture, and software teams to bring complex hardware to silicon readiness.

Location: Mountain View, California, United States — onsite

Salary: $250,000–$350,000 per year

Company

hirify.global is partnering with an early-stage AI hardware startup redesigning AI datacenter infrastructure and silicon.

What you will do

  • Own block- and SoC-level formal verification for AI accelerator silicon, from property development through proof convergence.
  • Develop SystemVerilog Assertions and formal verification environments for complex microarchitectural and system-level behavior.
  • Debug proof failures, identify root causes, and collaborate with RTL designers and architects to drive closure.
  • Build formal verification methodologies, infrastructure, and AI-assisted workflows, including AI agents for proof generation and convergence.
  • Apply formal techniques from early architectural validation through silicon bring-up readiness.
  • Partner with design, verification, and software teams to ensure scalable hardware.

Requirements

  • Master’s degree or equivalent experience and 8+ years of formal verification experience for complex SoCs.
  • Deep expertise in formal verification methodologies, including property authoring with SVA and/or PSL, proof strategies, abstraction, and convergence.
  • Strong experience debugging formal failures and working directly with RTL designers.
  • Hands-on experience with Synopsys VC Formal, Cadence JasperGold, or equivalent tools.
  • Strong understanding of modern digital design and microarchitecture.

Nice to have

  • Processor verification or security verification experience.
  • Equivalence checking, including LEC or SEC.
  • AMS verification or IP verification flow experience.
  • Experience building automation or AI-assisted verification workflows.

Culture & Benefits

  • Opportunity to own verification for critical AI accelerator hardware at an early-stage company.
  • Work on technically ambitious silicon with significant architectural influence.
  • Define next-generation AI-assisted formal verification methodologies.
  • Collaborate with a small, highly experienced team building AI infrastructure from the ground up.

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