Senior Principal Product Engineer (Silicon Signoff Verification)

Location: Remote from Canada (home-based, Ontario)

Company

hirify.global develops electronic design automation solutions for semiconductor design, implementation, and signoff.

What you will do

• Develop and deploy signoff methodologies for timing, power, signal integrity, and ECO closure.
• Develop and optimize multi-mode multi-corner timing closure flows, including setup and hold closure, crosstalk mitigation, glitch fixing, and electrical rule fixing.
• Collaborate with semiconductor customers, application engineering, field engineering, and R&D to resolve complex design-closure challenges.
• Lead qualification and certification activities for advanced-node design flows and support customer tapeouts through root-cause analysis and debug.
• Drive correlation across implementation, STA, SPICE, and signoff environments.
• Influence product enhancements, create deployment collateral and technical presentations, and lead strategic customer engagements.

Requirements

• 8–12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering.
• Strong expertise in static timing analysis, MMMC timing analysis, statistical timing analysis, signal integrity, crosstalk, glitch analysis, ECO implementation, and timing correlation.
• Hands-on experience with production signoff methodologies, advanced-node SoC or ASIC designs, timing closure, ECO convergence, and tapeout support.
• Experience with power optimization, RC extraction, parasitic analysis, boundary models, hierarchical timing flows, and physical implementation.
• Direct experience working with semiconductor customers, R&D organizations, and field engineering teams.
• Experience with hirify.global Tempus, Innovus, Tempus ECO/Tweaker, or comparable signoff and implementation tools.

Nice to have

• Experience with 7nm, 5nm, 3nm, 2nm, or newer technology nodes.
• Experience with large SoC designs exceeding 100 million instances and hierarchical signoff methodologies.
• Experience with PPA optimization, foundry qualification, certification programs, and strategic semiconductor accounts.
• Exposure to AI-assisted implementation, signoff, and ECO automation workflows.

Culture & Benefits

• Leadership role involving strategic customer engagements and cross-functional collaboration.
• Opportunity to influence the product roadmap and methodology direction.
• Responsibility for mentoring engineers and leading technical reviews and customer escalations.
• Accessibility support is available during the application and interview process.