Назад
Company hidden
32 минуты назад

Principal Product Engineer (High-Speed IP Memory)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
SK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Principal Product Engineer (High-Speed IP Memory): Driving customer-facing product engineering for high-performance memory and interface IP across pre-sales, SoC integration, post-silicon bring-up, and deployment with an accent on RTL, verification, timing closure, and subsystem integration. Focus on resolving complex customer issues, leading cross-functional technical reviews, improving debug efficiency with AI tools, and mentoring engineers.

Location: Gyeonggi-do (Seoul), South Korea

Company

hirify.global develops digital and mixed-signal IP solutions for high-performance semiconductor and interface applications.

What you will do

  • Own product engineering for memory subsystems including DDR, LPDDR, GDDR, and HBM at customer sites.
  • Lead customer engagements, technical discussions, design reviews, integration planning, and deployment strategy.
  • Resolve complex subsystem integration, implementation, and post-silicon debug issues through root-cause analysis.
  • Lead SoC integration reviews covering PHY and controller subsystems, including RTL, gate-level simulation, and timing closure strategies.
  • Improve integration methodologies, checklists, customer collateral, turnaround time, and engineering quality.
  • Collaborate with R&D, validation, and applications teams, use AI tools for debug and data analysis, and mentor junior engineers.

Requirements

  • Bachelor’s degree in electrical engineering, computer engineering, or a related field with 7+ years of experience; alternatively, a master’s degree with 5+ years or a PhD with relevant experience.
  • Strong experience with high-speed interface IP and deep knowledge of RTL design, gate-level verification, and simulation methodologies.
  • Experience with synthesis, static timing analysis, timing closure, DFT methodologies, test flows, and system validation.
  • Ability to solve complex technical problems, drive root cause to closure, and manage multiple priorities, escalations, and technical reviews.
  • Experience leading cross-functional efforts across design, validation, and customer teams, with strong communication and stakeholder influence.
  • Ability to work in Gyeonggi-do (Seoul), South Korea.

Nice to have

  • Experience with DDR, LPDDR, PCIe, Ethernet, UCIe, USB, or other high-speed communication interfaces.
  • Understanding of analog and mixed-signal design practices.
  • Experience with customer-facing silicon debug and bring-up environments.
  • Familiarity with AI-assisted workflows and data-driven debugging techniques.

Culture & Benefits

  • Work with global, cross-functional engineering teams.
  • Contribute to products supporting advanced digital and mixed-signal IP solutions.
  • Lead technical initiatives with direct customer impact and ownership across the product lifecycle.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →