5 дней назад
Analog Layout Intern (Semiconductor)
21 250 - 28 750€
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Analog Layout Intern (Semiconductor): Developing analog IC layouts in advanced CMOS technology nodes with an accent on CAD-based mask design, physical verification, and parasitic optimization. Focus on learning Cadence Virtuoso and Synopsys tools, running DRC/LVS checks, analyzing EMIR concepts, and optimizing area and parasitic resistance and capacitance.
Location: Pavia, Italy; internship takes place in the Pavia office
Expected base pay: €21,250–€28,750 annual rate
Company
develops semiconductor solutions and infrastructure technologies for enterprise, cloud, AI, carrier, storage, security, and networking applications.
What you will do
- Learn and use IC layout development CAD and physical verification tools.
- Design masks and layouts using Cadence Virtuoso EXL/Custom Compiler and Synopsys tools.
- Apply design rules for advanced CMOS technology nodes from 16nm to 3nm.
- Run DRC and LVS checks and learn EMIR concepts for analog IC layout.
- Optimize layouts for area and parasitic resistance and capacitance.
- Collaborate with analog, layout, and project teams, provide progress updates, and present issues or solutions.
Requirements
- Student of Electronics or a related technical field at an accredited Italian university, or a Bachelor’s/Master’s graduate.
- Fundamental understanding of electronic concepts and circuit elements, including diodes, transistors, capacitors, resistors, latches, flip-flops, and combinatorial logic.
- Fluency in English and sufficient Italian are required.
- Must be eligible to work in Italy without restrictions.
- Strong communication skills for status updates and presentations to global teams across different time zones.
Nice to have
- Coursework or training in analog design or layout.
- Exposure to IC design engineering skills and tools.
Culture & Benefits
- Up to six-month internship in a collaborative analog engineering team.
- Technical mentoring and regular meetings with the layout and project teams.
- Opportunities to learn new technologies and develop IC design skills.
- Shared collaboration, transparency, inclusivity, and professional development support.
- Access to technology and software may be subject to U.S. export control and licensing review.
Hiring process
- Interviews evaluate individual experience, thought process, and communication skills in real time.
- AI tools, transcription apps, answer generators, and automated note-taking tools are not permitted during interviews.
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