Analog IC Design Engineer, Intern (AI)

Location: Onsite at the hirify.global office in Pavia, Italy

Expected base pay: €21,250–€28,750 annual rate

Company

hirify.global develops semiconductor solutions and data infrastructure technologies for enterprise, cloud, AI, and carrier applications.

What you will do

• Design integrated circuits for electrical and electro-optical interfaces operating at 100+ Gb/s.
• Work with advanced 3nm FinFET and 2nm GAAFET technology nodes.
• Use Cadence and other CAD tools to design and simulate high-performance analog circuits.
• Develop skills in advanced analog and high-speed layout.
• Collaborate with the analog engineering team on effective design outcomes.

Requirements

• Bachelor’s degree in Electronics Engineering for an industrial Master Thesis, or current enrollment in a Master’s or PhD thesis.
• Academic knowledge of CMOS analog design and understanding of CMOS processes and fabrication.
• Basic knowledge of IC layout.
• Proficiency in spoken and written Italian and English at B2 level or higher.
• Strong written and verbal communication skills, self-motivation, willingness to learn, and ability to work effectively in a team.

Nice to have

• Basic knowledge of RF design techniques.

Culture & Benefits

• Six-month full-time contract at the Pavia office.
• Suitable for sponsorship of an industrial Master Thesis.
• Collaborative, transparent, and inclusive working environment.
• Access to tools and resources supporting professional development.
• Employment is subject to applicable U.S. export control eligibility and, where required, export license review.