Circuit Design Engineer (CMOS)

Location: 100% remote from any location; travel to Lexington, Massachusetts, up to 3 times per year if required by the program or project.

Company

hirify.global delivers IT and engineering solutions, including support for defense research organizations and secure, policy-compliant systems.

What you will do

• Implement physical layout and verification for integrated circuit building blocks.
• Assemble full-chip designs and perform top-level verification.
• Develop custom digital and mixed-signal readout integrated circuits for advanced imager applications.
• Apply layout techniques to manage local process variation and minimize unwanted parasitic interactions.
• Use high-speed digital and RF layout techniques within a multi-person design team.

Requirements

• Active Secret clearance or higher and US citizenship are required.
• At least 10 years of experience with Cadence IC design flow, including layout, DRC, LVS, and parasitic extraction using Calibre and Assura.
• At least 10 years of experience in top-level floor planning, block-level design, and multiple design tape-outs.
• Deep-submicron CMOS layout experience across 12–65 nm design nodes and foundries including GlobalFoundries, onsemi, and TowerJazz.
• Strong written, verbal, interpersonal, organizational, and team communication skills.
• The role is part time, up to 24 hours per week.

Culture & Benefits

• Remote work from any location.
• Up to 3+ trips per calendar year to Lexington when required by the program or project.
• Part-time schedule of up to 24 hours per week.
• Work focused on advanced defense research and imager circuit development.

Hiring process

• First-round Zoom interview with the hiring manager.
• Second-round Zoom interview with additional team members as needed.