Advanced Package Technology, Principal Engineer (Semiconductor)

Location: Hsinchu City, Taiwan

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, and networking data infrastructure.

What you will do

• Develop packaging technology roadmaps for AI XPUs, XPU-attach solutions, and switches.
• Create advanced package technology concepts, evaluate routing feasibility, run signal and power integrity studies, and develop proof-of-concept samples into productizable technologies.
• Define package architecture, including chiplet topology, interposer and substrate scaling, power delivery networks, and thermal design envelopes.
• Lead co-design across silicon design, floorplanning, PDN modeling, and mechanical and thermal reliability.
• Define package materials and substrate stack-ups, perform mechanical and reliability analysis, and optimize die floorplans, bump maps, TSVs, and RDL requirements.
• Work with OSATs and foundry partners on process capability, manufacturability, yield, cost, qualification, and reliability validation through volume readiness.

Requirements

• Advanced package and substrate technology experience, including process, materials, component and board-level reliability, warpage, and thermal management.
• Deep knowledge of electrical engineering, circuit extraction and simulation, signal and power integrity, transmission lines, and electromigration.
• Hands-on experience with 2.5D and 3D package analysis using Cadence Sigrity PowerSI, Ansys SIwave, Ansys HFSS, SI-Wave, and Cadence Clarity.
• Experience with interposer, substrate, package, and PCB design rules and routing feasibility using Cadence APD or PCB Editor.
• Bachelor’s or master’s degree in mechanical engineering, materials science, or a related field with 8–10 years of professional experience, or a PhD/postdoctoral background with 5+ years of experience.
• Ability to manage cross-functional programs, influence vendors, and communicate effectively with stakeholders across multiple time zones.

Nice to have

• Experience with data center AI accelerators, networking silicon, custom HPC silicon, and board, system, or rack-level integration.
• Experience with silicon disaggregation and reaggregation, memory integration, supplier programs, and technology roadmaps.
• Experience using VNA and TDR measurements for package and PCB characterization.

Culture & Benefits

• Eligibility for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Competitive compensation and benefits in a collaborative, transparent, and inclusive work environment.
• Resources and development opportunities to support professional growth.
• Access to export-controlled technology may require eligibility under U.S. export control laws and an export license review for some applicants.
• AI tools are not permitted during interviews.