Senior Physical Design AI/ML Engineer, Logic Pathfinding Lab (AI)

Location: Daily onsite presence at the San Jose office/headquarters, United States

Base pay: $138,000–$206,000 USD annually, plus incentive opportunities.

Company

hirify.global develops technology solutions for smartphones, electric vehicles, hyperscale data centers, IoT devices, and other advanced applications.

What you will do

• Design, build, and implement machine learning and generative models that optimize chip layout designs for performance, power, and area efficiency.
• Automate design implementation workflows including floor-planning, placement and routing, and clock tree synthesis using exploratory PDKs.
• Automate verification workflows including Design Rule Checks and Layout versus Schematic checks.
• Automate exploratory PDK generation and develop automated QA systems.
• Apply machine learning to correlate device, ring oscillator benchmark, and circuit-block data across operating conditions.
• Develop internal benchmarking and assessment capabilities for the R&D organization.

Requirements

• PhD with industry experience preferred.
• Experience with RTL synthesis, place and route, timing analysis, and clock and power delivery networks.
• Hands-on experience with machine learning or deep learning for scientific or engineering applications, including regression, surrogate modeling, inverse design, or graph neural networks.
• Strong Python and/or C++ skills, including experience with PyTorch and TensorFlow.
• Experience with Bayesian optimization and/or active learning for design-space exploration.
• Experience with agentic AI frameworks such as LangGraph, CrewAI, or ADK.

Nice to have

• Experience optimizing design-technology co-optimization knobs for advanced logic nodes, especially 2nm or beyond.
• Familiarity with AI workloads and their compute and memory requirements.
• Experience setting up and optimizing a private compute cluster for current LLM models.
• Proficiency with EDA tools for synthesis and layout, and experience using generative AI for chip design optimization.

Culture & Benefits

• Inclusive, diverse, and collaborative work environment with opportunities to guide multiple organizations and research consortia.
• Medical, dental, vision, and 401(k) benefits.
• 4+ weeks of paid time off annually, plus holidays and sick leave.
• Family support programs, emotional wellness resources, and fitness facilities including an onsite café and gym.
• Flexible work environment aligned with daily onsite work requirements.